 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| STK11C68 (SMD5962-92324) 8Kx8 SoftStore nvSRAM FEATURES * 25, 35, 45, and 55 ns Read Access & R/W Cycle Times * Unlimited Read/Write Endurance * Pin compatible with Industry Standard SRAMs * Software-initiated Non-Volatile STORE * Automatic RECALL to SRAM on Power Up * Unlimited RECALL cycles * 1 Million STORE Cycles * 100-Year Non-volatile Data Retention * Single 5V + 10% Operation * Commercial, Industrial, and Military Temperatures * 28 pin 330 mil SOIC (RoHS-Compatible) * 28-pin CDIP and LCC packages DESCRIPTION The Simtek STK11C68 is a 64Kb fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use, and unlimited read & write endurance of a normal SRAM. Data transfers under software control to the non-volatile storage cells (the STORE operation). On power-up, data is automatically restored to the SRAM (the RECALL operation). RECALL operations are also available under software control. The Simtek nvSRAM is the first monolithic nonvolatile memory to offer unlimited writes and reads. It is the highest performance, most reliable nonvolatile memory available. BLOCK DIAGRAM BLOCK DIAGRAM QUANTUM TRAP 128 x 512 ROW DECODER A5 A6 A7 A8 A9 A11 A12 STORE STATIC RAM ARRAY 128 X 512 RECALL STORE/ RECALL CONTROL SOFTWARE DETECT DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A0 - A12 INPUT BUFFERS COLUMN I/O COLUMN DEC A 0 A 1 A 2 A 3 A 4 A10 G E W This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status. 1 Document Control #ML0007 Rev 0.3 February, 2007 STK11C68 (SMD5962-92324) PIN CONFIGURATIONS NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28-Pin LCC 28-Pin DIP 28-Pin SOIC PIN NAMES Pin Name A12-A0 DQ7-DQ0 E W G VCC VSS Input I/O Input Input Input Power Supply Power Supply I/O Description Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array Data: Bi-directional 8-bit data bus for accessing the nvSRAM Chip Enable: The active low E input selects the device Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. Power: 5.0V, 10% Ground Document Control #ML0007 Rev 0.3 February, 2007 2 STK11C68 (SMD5962-92324) ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . .-0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTERISTICS COMMERCIAL SYMBOL ICC1b PARAMETER MIN Average VCC Current MAX 90 75 65 N/A 3 10 27 23 20 N/A 750 1 5 2.2 VSS - .5 2.4 0.4 0 70 -40 VCC + .5 0.8 2.2 INDUSTRIAL/ MILITARY MIN MAX 90 75 65 55 3 10 28 24 21 20 1500 1 5 mA mA mA mA mA mA mA mA mA mA A A A UNITS (VCC = 5.0V 10%) NOTES tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels tAVAV = 25ns, E VIH tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH tAVAV = 55ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA IOUT = 8mA ICC2c ICC3b ISB1d Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25C, Typical Average VCC Current (Standby, Cycling TTL Input Levels) ISB2d IILK IOLK VIH VIL VOH VOL TA VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature VCC + .5 V V V 0.4 85 V C VSS - .5 0.8 2.4 Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC is the average current required for the duration of the STORE cycle (tSTORE ) . 2 Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 5.0V 480 Ohms OUTPUT 255 Ohms CAPACITANCEe SYMBOL CIN COUT PARAMETER Input capacitance (TA = 25C, f = 1.0MHz) MAX 8 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V 30 pF INCLUDING SCOPE AND FIXTURE Output Capacitance Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading Document Control #ML0007 Rev 0.3 February, 2007 3 STK11C68 (SMD5962-92324) SRAM READ CYCLES #1 & #2 SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 PARAMETER #1, #2 tELQV tAVAVf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZ h (VCC = 5.0V + 10%) STK11C68-25 STK11C68-35 MIN MAX 35 35 25 10 5 5 10 0 10 0 25 0 35 0 13 0 45 5 5 13 0 15 0 55 35 15 5 5 15 0 25 45 45 20 5 5 25 STK11C68-45 MIN MAX 45 55 55 25 STK11C68-55 UNITS MIN MAX 25 25 MIN MAX 55 ns ns ns ns ns ns ns ns ns ns ns Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby tELICCHe tEHICCL d, e Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g tAVAV ADDRESS 5 3 2 tAVQV DATA VALID tAXQX DQ (DATA OUT) SRAM READ CYCLE #2: E Controlledf tAVAV ADDRESS tELQV E 6 tELQX 7 1 2 tEHICCL 11 tEHQZ G tGLQV 4 tGHQZ 9 tGLQX DQ (DATA OUT) 10 tELICCH DATA VALID 8 ACTIVE ICC STANDBY Document Control #ML0007 Rev 0.3 February, 2007 4 STK11C68 (SMD5962-92324) SRAM WRITE CYCLES #1 & #2 SYMBOLS NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ h, i (VCC = 5.0V + 10%) STK11C68-25 STK11C68-35 MIN 35 25 25 12 0 25 0 0 10 5 5 13 5 MAX STK11C68-45 MIN 45 30 30 15 0 30 0 0 15 5 MAX STK11C68-55 UNITS MIN MAX MIN 55 45 45 30 0 45 0 0 35 MAX ns ns ns ns ns ns ns ns ns ns 25 20 20 10 0 20 0 0 PARAMETER #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write tWHQX Note i: Note j: If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledj 12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ PREVIOUS DATA DATA VALID 19 tWHAX 18 tAVWL W 16 tWHDX DATA OUT HIGH IMPEDANCE 21 tWHQX SRAM WRITE CYCLE #2: E Controlledj 12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX 17 tAVEH W 13 tWLEH 15 tDVEH 16 tEHDX DATA VALID HIGH IMPEDANCE DATA IN DATA OUT Document Control #ML0007 Rev 0.3 February, 2007 5 STK11C68 (SMD5962-92324) STORE INHIBIT/POWER-UP RECALL SYMBOLS NO. Standard 22 23 24 25 tRESTORE tSTORE VSWITCH VRESET Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level Low Voltage Reset Level 4.0 PARAMETER MIN MAX 550 10 4.5 3.6 s ms V V k (VCC = 5.0V + 10%) STK11C68 UNITS NOTES Note k: tRESTORE starts from the time VCC rises above VSWITCH. STORE INHIBIT/POWER-UP RECALL VCC 5V 24 VSWITCH 25 VRESET STORE INHIBIT POWER-UP RECALL 22 tRESTORE DQ (DATA OUT) POWER-UP RECALL BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT STORE INHIBIT RECALL WHEN VCC RETURNS ABOVE VSWITCH Document Control #ML0007 Rev 0.3 February, 2007 6 STK11C68 (SMD5962-92324) SOFTWARE STORE/RECALL MODE SELECTION E W A12 - A0 (hex) 0000 1555 0AAA 1FFF 10F0 0F0F 0000 1555 0AAA 1FFF 10F0 0F0E MODE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z NOTES L H l L H l Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. SOFTWARE STORE/RECALL CYCLEm, n STK11C68-25 NO. 26 27 28 29 30 SYMBOLS tAVAV tAVEL m (VCC = 5.0V 10%) STK11C68-35 MIN 35 0 25 20 20 20 MAX STK11C68-45 MIN 45 0 30 20 20 MAX STK11C68-55 UNITS MIN 55 0 35 20 20 MAX ns ns ns ns s MAX PARAMETER MIN STORE/RECALL Initiation Cycle Time Address Set-up Time Clock Pulse Width Address Hold Time RECALL Duration 25 0 20 20 tELEHm tELAXm tRECALLm Note m: The software sequence is clocked with E controlled reads. Note n: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledn tAVAV ADDRESS 27 ADDRESS #1 26 tAVAV ADDRESS #6 26 tAVEL E tELEH 28 tELAX 23 30 / tRECALL 29 tSTORE DQ (DATA DATA VALID DATA VALID HIGH IMPEDANCE Document Control #ML0007 Rev 0.3 February, 2007 7 STK11C68 (SMD5962-92324) DEVICE OPERATION The STK11C68 is a versatile memory chip that provides several modes of operation. The STK11C68 can operate as a standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements shadow to which the SRAM information can be copied or from which the SRAM can be updated in nonvolatile mode. SOFTWARE NONVOLATILE STORE The STK11C68 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle NOISE CONSIDERATIONS Note that the STK11C68 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between Vcc and Vss, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK11C68 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-12 determines which of the 8,192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high. The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle Document Control #ML0007 Rev 0.3 February, 2007 8 STK11C68 (SMD5962-92324) Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Elements. The nonvolatile data can be recalled an unlimited number of times. HARDWARE PROTECT The STK11C68 offers hardware protection against inadvertent STORE operation during low-voltage conditions. When VCC < VSWITCH, software STORE operations are inhibited. LOW AVERAGE ACTIVE POWER The STK11C68 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK11C68 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. 100 POWER-UP RECALL During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK11C68 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC. 100 Average Active Current (mA) Average Active Current (mA) 80 80 60 60 TTL CMOS 20 40 TTL 20 CMOS 0 50 100 150 Cycle Time (ns) 200 40 0 50 100 150 Cycle Time (ns) 200 Figure 2: ICC (max) Reads Figure 3: ICC (max) Writes Document Control #ML0007 Rev 0.3 February, 2007 9 STK11C68 (SMD5962-92324) Commercial/Industrial Ordering Information STK11C68 - S F 45 I TR Temperature Range Blank = Tube TR = Tape and Reel Temperature Range Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Lead Finish F = 100% Sn (Matte Tin) Package S = Plastic 28-pin 330 mil SOIC C = Ceramic 28-pin 300 mil DIP L = Ceramic 28-pin 350 mil LCC Document Control #ML0007 Rev 0.3 February, 2007 10 STK11C68 (SMD5962-92324) Millitary Ordering Information STK11C68 - 5 C 45 M Temperature Range M = Military (-55 to 125C) Access Time 35 = 35ns 45 = 45ns 55 = 55ns Package C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (solder dip finish) L = Ceramic 28 pin LCC Retention / Endurance 5 = Military (10 years/105cycles) SMD5962-92324 04 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish "A" or "C" is acceptable Package MX = Ceramic 28 pin 300-mil DIP MY = Ceramic 28 pin LCC Device Class Indication--Class M Access Time 04 = 55ns 05 = 45ns 06 = 35ns Document Control #ML0007 Rev 0.3 February, 2007 11 STK11C68 (SMD5962-92324) Ordering Information Part Number STK11C68-SF25 STK11C68-SF35 STK11C68-SF45 STK11C68-SF25TR STK11C68-SF35TR STK11C68-SF45TR STK11C68-L35 STK11C68-L45 STK11C68-C35 STK11C68-C45 STK11C68-SF25I STK11C68-SF35I STK11C68-SF45I STK11C68-SF25ITR STK11C68-SF35ITR STK11C68-SF45ITR STK11C68-L35I STK11C68-L45I STK11C68-C35I STK11C68-C45I STK11C68-5L35M STK11C68-5L45M STK11C68-5L55M STK11C68-5C35M STK11C68-5C45M STK11C68-5C55M STK11C68-5K35M STK11C68-5K45M STK11C68-5K55M SMD5962-9232406MXA SMD 5962-9232405MXA SMD 5962-9232404MXA SMD 5962-9232406MXC SMD 5962-9232405MXC SMD 5962-9232404MXC SMD 5962-9232406MXX SMD 5962-9232405MXX SMD 5962-9232404MXX SMD 5962-9232406MYA SMD 5962-9232405MYA SMD 5962-9232404MYA SMD 5962-9232406MYX SMD 5962-9232405MYX SMD 5962-9232404MYX Description 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM SOP28-330 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CDIP28-300 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 5V 64K-8b SoftStore nvSRAM CLCC28 Temperature Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Document Control #ML0007 Rev 0.3 February, 2007 12 STK11C68 (SMD5962-92324) Package Diagrams 28 Pin 330 mil SOIC 0.713 0.733 ( 18.11 ) 18.62 0.112 (2.845) 0.004 (0.102) 0.020 0.014 ( 0.508 ) 0.356 0.050 (1.270) 0.103 0.093 ( 2.616 ) 2.362 0.336 0.326 ( 8.534 ) 8.280 Pin 1 0.477 0.453 ( 12.116 ) 11.506 0.014 0.008 ( 0.356 ) 0.203 0.044 0.028 10 0 ( 1.117 ) 0.711 DIM = INCHES DIM = mm MIN MAX MIN ( MAX ) Document Control #ML0007 Rev 0.3 February, 2007 13 STK11C68 (SMD5962-92324) 28 Pin 300 mil SP DIL Sidebraze 1.386 1.414 35.20 (35.92) .280 .310 (7.36) 7.87 --.060 --(1.52 ) PIN 14 ( 3.15 ).124 4.14 .162 .125 (3.18) MIN .040 .060 (1.02) 1.52 .016 .020 () 0.41 0.51 .048 .052 () 1.22 1.32 .090 2.29 .110 2.79 () .290 .310 ( 7.37 ) 7.87 DIM = INCHES DIM = mm MIN MAX MIN ( MAX ) .009 .012 ( 0.23 ) 0.30 .300 .320 (7.62) 8.13 Document Control #ML0007 Rev 0.3 February, 2007 14 STK11C68 (SMD5962-92324) 28 Pin 350 mil LCC 0.542 13.77 0.558 14.17 ( ) (1.02) 0.040 REF X 45 3 places 0.342 8.69 0.358 9.09 ( ) (0.51) 0.020 REF X 45 0.075 0.095 (0.23) 0.009 REF 28 places 1.91 ( 2.41 ) 0.045 1.14 0.055 ( 1.40 ) Pad 1 Index ( 0.022 0.028 0.56 0.71 )( 0.006 0.022 0.15 0.56 ) 0.045 0.055 ( 1.14 ) 1.40 0.070 1.78 0.090 2.29 ( ( ) 0.062 1.57 0.078 1.98 0.015 --0.381 --- ) --0.558 --( 14.17 ) ( ) DIM = INCHES DIM = mm MIN MAX MIN ( MAX ) Document Control #ML0007 Rev 0.3 February, 2007 15 STK11C68 (SMD5962-92324) Document Revision History Revision 0.0 0.1 0.2 0.3 Date December 2002 September 2003 March 2006 February 2007 Summary Combined commercial, industrial and military data sheets. Removed 20 nsec device. Added lead-free lead finish Removed leaded lead finish for all Commercial/Industrial Parts, Removed "P" package. Add fast power-down slew RSK information Restore Comm/Ind C & L Package Options Add Tape Reel Ordering Options Add Product Ordering Code Listing Add Package Outline Drawings Reformat Entire Document SIMTEK STK11C68 Datasheet, February 2007 Copyright 2007, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right. Document Control #ML0007 Rev 0.3 February, 2007 16 |
Price & Availability of STK11C68-SF45TR
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |